There are various types of nonvolatile memory, such as flash memories, ferroelectric random-access memories, and magnetoresistive random access memories. The flash memories are broadly classified into NAND flash memories and NOR flash memories. Since the NAND flash memories make it easier to increase the degree of integration because of their structures, the NAND flash memories are used in large-capacity storage devices, typified by solid-state drives (SSDs). On the other hand, the NOR flash memories are used for storing Basic Input/Output Systems (BIOSs), logs, field programmable gate array (FPGA) configuration data, and so on.
In the case of SSDs using NAND flash memories, built-in SSD controllers ensure the reliability during operation. NOR flash memories are mostly used alone, and memory devices having error correction functions are available, but a failure, such as logic inversion, may occur during operation.
In flash memories, a write duration varies greatly from one memory cell to another, for example, owing to the dimension of a control gate, variations in impurity concentration in source and drain regions, a defect during manufacture of a floating gate, an insulating layer, and so on. Thus, in a process of testing for shipment, a write reference voltage is adjusted for each unit of writing (for example, for each bit, word, or block) to converge write durations into a certain range.
However, since the adjustment width of the write reference voltage is limited, there is a certain degree of variations in the write durations after adjusting the write times. With respect to memory cells whose original variations in manufacture are small, the write durations can be adjusted so as to be positioned in the vicinity of a center value (a reference value) of the write durations, which provides memory cells having no problem with memory characteristics.
On the other hand, with respect to memory cells whose original variations in manufacture are significantly large, the write durations are not adjustable so as to fit within a predetermined specified range in which the center value is located, and the memory cells are handled as defective cells. Addresses corresponding to such memory cells may be remedied by performing processing, such as replacing the memory cells with auxiliary memory cells through redundancy processing. When the number of defective cells is large to a degree that the remedy is not possible, the memory device itself is discarded as a defective product.
With respect to a memory cell whose original variations in manufacture are large to a certain degree, not to the above-described degree that the cell in question is handled as a defective cell, the write duration is adjustable so as to fit within the above-described predetermined specified range, but the write duration deviates from the center value significantly. Such a memory cell has a high degree of defectiveness in the memory characteristics and has a possibility that there is a problem with the data retention characteristic. That is, electrical charge accumulated in a floating gate is discharged with time, which may cause loss of stored data.
Even in a memory device including a memory cell having a problem in the data retention characteristic, as described above, when all memory cells fit in the predetermined specified range, a write duration reference in testing for shipment is satisfied, and thus the memory device is shipped from a memory maker as a non-defective product. The problem in the data retention characteristic in such a memory device becomes evident during actual operation after a set maker (a manufacturer that purchases components, such as memory devices, to manufacture products and sell the products to end consumers) build the component into an apparatus. It is problematic for the set maker to be able to notice a failure in the data retention characteristic only after a product into which a potentially problematic memory device is built is shipped to the market.
A technique in which a memory device to which data has been written is placed, for example, in a high temperature state at 125° C. for 24 hours and elapse of a time, for example, one year, in terms of a typical operating state is simulated to detect a potential problem in the data retention characteristic of the memory device is also possible, that is, accelerated screening is also possible. However, even the accelerated screening involves processing in which the high temperature state is continued for 24 hours or more, and taking a large amount of time is a problem.
Hence, it is desirable that a memory cell that is likely to have a problem in the data retention characteristic in a nonvolatile memory be identifiable during writing of actual data.
The followings are reference documents.    [Document 1] Japanese Laid-open Patent Publication No. 2008-262614,    [Document 2] Japanese Laid-open Patent Publication No. 2012-133865,    [Document 3] Japanese Laid-open Patent Publication No. 2008-117500, and    [Document 4] International Publication Pamphlet No. WO2007/066523.